1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to approaches for spacer chamfering for a replacement metal gate (RMG) device.
2. Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., fin field effect transistors (FinFETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FinFET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FinFET includes a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition, etc.
Silicon based FinFETs have been successfully fabricated using conventional MOSFET technology. A typical FinFET is fabricated on a substrate with an overlying insulating layer with a thin ‘fin’ extending from the substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A single or double gate is provided over the fin(s). A double gate is beneficial in that there is a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of FinFETs include reducing the short channel effect and higher current flow. Other FinFET architectures may include three or more effective gates.
As FinFETs continue to shrink in size (e.g., 10 nm and beyond), a work-function metal chamfering process is necessary to achieve a desired threshold voltage (Vth). However, the nominal gate conductor (PC) critical dimension (CD) is challenging for the chamfering process and subsequent metal fill process at this device size. Prior art approaches have attempted to widen the spacer using a spacer inner etch (i.e., a poly pull back) for a portion of the spacer.
This is shown in FIG. 1 in which prior art device 10 comprises a set of finFETs 12 formed over a substrate 14 and a source trench isolation (STI) material 16. Spacers 18 are formed along each FinFET 12. As demonstrated in prior art device 10 of FIG. 2, a half poly pull back is performed to remove polysilicon 20 and a portion of spacers 18. However, this approach suffers from a number of drawbacks. First, this process is difficult to control because the polysilicon reactive ion etch (RIE) must be controlled by time, which produces poor uniformity within the wafer and negatively influences yield. Second, a poly overetch may lead to fin damage, which degrades overall device performance. Third, this approach only widens the spacer above each finFET 12, but does not widen the region below the fin to maintain the gate CD, which is critical for work-function metal deposition.